Epoch AI reports top chip designers used about 90% of HBM and CoWoS supply in 2025

• Epoch AI’s supply-chain estimate says NVIDIA, Google, AMD, and Amazon together used roughly 90% of global CoWoS advanced packaging and high-bandwidth memory in 2025, making those components the likely bottlenecks for frontier AI chip output.
• In Epoch’s methods thread, the constraint is not leading-edge logic wafers: AI chips accounted for only about 12% of advanced logic supply in 2025, while packaging and HBM were “almost entirely consumed by AI demand.”
• The breakout chart is especially lopsided for NVIDIA, which Epoch estimates took 60% of CoWoS capacity and 69% of HBM by value, with confidence intervals showing the same basic picture even under uncertainty.
• Meta’s MTIA roadmap and NVIDIA’s open-weight model push show why this matters beyond one report: hyperscalers are expanding both custom silicon and model ambitions into a supply chain Epoch argues was already saturated.

Epoch’s estimate is that packaging and memory, not logic dies, were the hard constraint on AI chip production in 2025. In the main thread, it says the four largest AI chip designers consumed about 90% of global CoWoS packaging and HBM supply by value, while advanced logic remained broadly available to other markets such as phones, laptops, and automotive.

The methodology post adds the reproducible part engineers will care about: Epoch built the estimate from chip technical specs, unit costs, market-size data, its AI Chip Sales hub, and a model for manufacturing lags and inventory timing. It also links to the full data insight and SemiAnalysis context for deeper methodology and industry background.

The distribution is highly concentrated. According to Epoch’s chart breakdown, NVIDIA alone accounted for 60% of CoWoS consumption and 69% of HBM consumption in 2025, versus much smaller shares for Google, AMD, and Amazon. By contrast, AI chip designers together used only 12% of advanced logic supply, which is why Epoch argues “advanced packaging and HBM — not logic dies — were the bottlenecks.”

If Epoch’s estimate is directionally right, compute planning is increasingly a memory-and-packaging problem, not just a foundry-node problem. That changes how engineers should interpret capacity announcements: new accelerators do not translate cleanly into deployable inference or training volume if HBM stacks and CoWoS lines remain the scarce inputs.

Meta’s MTIA plan makes that concrete. The company says it is developing and deploying “four new generations” of MTIA chips within two years, with MTIA 300 already in production for ranking and recommendations and MTIA 400/450/500 aimed at GenAI inference and training through 2027. Its MTIA coverage frames the push as reducing dependence on external vendors while improving “performance-per-watt” for Meta’s own workloads.

NVIDIA is also moving up the stack. The filings summary says it plans to invest $26 billion over five years to build open-weight AI models, which would put the same company that dominates accelerator supply deeper into model competition. That combination matters because the firms setting model and platform strategy are also the ones competing most aggressively for the constrained components Epoch identified.