Google launches TPU 8tx and 8i Max inference systems

• TPU 8tx pairs existing 8t silicon with AMD processors for confidential inference, as WesRoth explains.
• TPU 8i Max packages two 8i chips together for long-context workloads, according to WesRoth's breakdown.
• The accompanying performance chart covers TPU7x versus GB200 NVL72, with provisional results in the attached benchmark.

Four TPU systems from two chip designs is a tidy bit of systems engineering. The November 9 launch also includes TPU Sync, which turns host memory and storage into tiers for KV-cache offload.

Google now has nearly 100 TPU customers, and some regulated customers specifically requested protection for data during processing.

According to Google's announcement, the 8tx combines:

• Existing compute silicon: TPU 8t chips paired with fifth-generation AMD EPYC CPU hosts.
• Confidential processing: Hardware-level protection and isolation for sensitive data and model weights while in use, with what Google calls a “near-zero performance penalty.”
• A different interconnect: The low-latency Boardfly network developed for real-time reasoning. Google claims up to 2x lower latency than TPU 8t.
• Local model customization: Inference, private fine-tuning, distillation and reinforcement learning on one system, avoiding transfers of sensitive data between separate training and serving clusters.

Two TPU 8i chips share one package, extending the reasoning-oriented design Google introduced in April.

Google's product specifications describe three increases over TPU 8i:

• Compute: 2x.
• SRAM: 2x.
• HBM bandwidth: 2x.

Google says the configuration fits twice the silicon within the existing rack footprint. The launch post supplies no absolute HBM-capacity or bandwidth figures for Max.

Neither new system receives pricing or a general-availability date in the announcement.

SemiAnalysis names GB300 NVL72 in its launch-day post. The attached InferenceX chart labels Nvidia's configuration GB200 NVL72 and Google's TPU7x, both running SGLang.

The cost model uses July 2026 pricing assumptions: $1.21 per TPU7x chip-hour and $1.86 per GB200 chip-hour. SemiAnalysis says improvements across the TPUv7 inference stack can transfer at a high level to TPUv8; the chart's tooltip says results may change during validation and publication.

• Native PyTorch serving: Google's TorchTPU-backed vLLM and SGLang engines launched October 20, developed with Inferact and RadixArk, respectively. TorchTPU uses standard PyTorch tensors on a tpu device, with eager execution or torch.compile through XLA.
• Asynchronous state movement: The new TPU Sync library is open-source native C++. It moves TPU-tiled tensors using asynchronous DMA transfers that overlap data movement with computation.
• Storage-backed KV caches: TPU Sync coordinates accelerator HBM, host DRAM, shared storage and the data-center network. Its automated cache tiers include host memory, local SSDs and Google Cloud Managed Lustre; its lower-level primitives also support streaming updated weights from RL trainers to samplers.